Observe Idss 10.0* 50.0*. See the note. They come in AK(6,7,8) 3 different ranges of Idss. The 10 - 50 being broken into three pieces. Mine are AK7 which is 16 - 32 ma. It is good to know I can pass that much current without damaging my JFETs but I like to not drain my batteries any more than necessary. My goal will be less than 1 ma for each stage. The JFET can be looked at as a voltage controlled current source. It has a self regulated current when the gate is tied to the source and when the gate is biased with a set voltage it will regulate at a different current. So the problem is to determine at what voltage to set the gate. Fortunately the device will find a point of operation on its own if we just provide the bias and we can provide a negative feedback by simply placing a resistor in the source circuit with the gate tied to the other end. The Vgs(off) or pinch off voltage is also on the sheet above. -0.6 to -3.0 volts with -1.4 volt typical. So I GUESS I can place a 2.2k resistor in the source circuit and get a drain current well below 1 ma. Now to the sim.
Here I placed a capacitor in both circuits and they are identical except for being out of phase.
If you have a 2k headphone you can use this circuit. Here again make no difference if it is fed from the source or drain. Why is this? We have the same current flowing through the resistor s and they are the same value. What would happen if we raise the drain resistor value?
How about the other drain resistors???
You may have noticed I used 2SK117s in the sim. I don't have a SPICE model for the 2SK2539. My next project will be to build a model that more closely matches my circuit.
To be continued..............
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